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TVLSI
2008
133views more  TVLSI 2008»
15 years 4 months ago
A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance
Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fi...
Mitchell J. Myjak, José G. Delgado-Frias
TVLSI
2008
111views more  TVLSI 2008»
15 years 4 months ago
GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering
This paper describes Glitchless, a circuit-level technique for reducing power in FPGAs by eliminating unnecessary logic transitions called glitches. This is done by adding program...
Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wil...
TVLSI
2008
197views more  TVLSI 2008»
15 years 4 months ago
Leakage Minimization of SRAM Cells in a Dual-Vt and Dual-Tox Technology
-- Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in deep submicron regime. As a result, reducing the subthreshold a...
Behnam Amelifard, Farzan Fallah, Massoud Pedram
TVLSI
2008
207views more  TVLSI 2008»
15 years 4 months ago
Effective Radii of On-Chip Decoupling Capacitors
Decoupling capacitors are widely used to reduce power supply noise. On-chip decoupling capacitors have traditionally been allocated into the white space available on a die or place...
Mikhail Popovich, Michael Sotman, Avinoam Kolodny,...
TWC
2008
137views more  TWC 2008»
15 years 4 months ago
Decoding, Performance Analysis, and Optimal Signal Designs for Coordinate Interleaved Orthogonal Designs
Space-time block codes (STBC) using coordinate interleaved orthogonal designs (CIOD) proposed recently by Khan and Rajan allow single-complex symbol decoding and offer higher data ...
Dung Ngoc Dao, Chintha Tellambura
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