48 search results - page 6 / 10 » Boolean satisfiability in electronic design automation |
DAC
2005
ACM
16 years 1 months ago
2005
ACM
This paper attempts to quantify the optimality of FPGA technology mapping algorithms. We develop an algorithm, based on Boolean satisfiability (SAT), that is able to map a small s...
DAC
2005
ACM
16 years 1 months ago
2005
ACM
SAT (Boolean satisfiability) has become the primary Boolean reasoning engine for many EDA applications, so the efficiency of SAT solving is of great practical importance. Recently...
DAC
2006
ACM
16 years 1 months ago
2006
ACM
Most FPGA technology mapping approaches either target Lookup Tables (LUTs) or relatively simple Programmable Logic Blocks (PLBs). Considering networks of PLBs during technology map...
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DAC
2002
ACM
16 years 1 months ago
2002
ACM
Research in algorithms for Boolean satisfiability and their efficient implementations [26, 8] has recently outpaced benchmarking efforts. Most of the classic DIMACS benchmarks fro...
100
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DAC
2004
ACM
16 years 1 months ago
2004
ACM
Instances of the Boolean satisfiability problem (SAT) arise in many areas of circuit design and verification. These instances are typically constructed from some human-designed ar...