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118
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CODES
2003
IEEE
15 years 5 months ago
2003
IEEE
This paper presents a software implementation of a very fast parallel Reed-Solomon decoder on the second generation of MorphoSys reconfigurable computation platform, which is targ...
ISCAS
2006
IEEE
15 years 5 months ago
2006
IEEE
—This paper describes a low cost, low power, versatile computation module that can be used as a coarse-grain building block in multimedia processors. The module, which has a data...
82
Voted
ASAP
2002
IEEE
15 years 4 months ago
2002
IEEE
The determinism of instruction cache performance can be considered a major problem in multi-media devices which hope to maximise their quality of service. If instructions are evic...
ESTIMEDIA
2006
Springer
15 years 3 months ago
2006
Springer
Nowadays, key characteristics of a processor's instruction set are only exploited in high-level languages by using inline assembly or compiler intrinsics. Inserting intrinsic...
195
Voted
ASPLOS
2009
ACM
16 years 9 days ago
2009
ACM
Parallel bit stream algorithms exploit the SWAR (SIMD within a register) capabilities of commodity processors in high-performance text processing applications such as UTF8 to UTF-...