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STACS
2000
Springer
15 years 9 months ago
The Complexity of Planarity Testing
We clarify the computational complexity of planarity testing, by showing that planarity testing is hard for L, and lies in SL. This nearly settles the question, since it is widely...
Eric Allender, Meena Mahajan
176
Voted
DAC
2005
ACM
15 years 8 months ago
Template-driven parasitic-aware optimization of analog integrated circuit layouts
Layout parasitics have great impact on analog circuit performance. This paper presents an algorithm for explicit parasitic control during layout retargeting of analog integrated c...
Sambuddha Bhattacharya, Nuttorn Jangkrajarng, C.-J...
180
Voted
EJC
2006
15 years 6 months ago
A note on Ramsey numbers with two parameters
1 The Ramsey number R(G1, G2) is the smallest integer p such that for any graph G on p vertices2 either G contains G1 or G contains G2, where G denotes the complement of G. In this...
Yi Ru Huang, Jian Sheng Yang, Kemin Zhang
CORR
2007
Springer
85views Education» more  CORR 2007»
15 years 6 months ago
A multivariate interlace polynomial
We define a multivariate polynomial that generalizes in a unified way the twovariable interlace polynomial defined by Arratia, Bollob´as and Sorkin on the one hand, and a one-...
Bruno Courcelle
VLSISP
2008
111views more  VLSISP 2008»
15 years 6 months ago
Design Methodology for Throughput Optimum Architectures of Hash Algorithms of the MD4-class
Abstract. In this paper we propose an architecture design methodology to optimize the throughput of MD4-based hash algorithms. The proposed methodology includes an iteration bound ...
Yong Ki Lee, Herwin Chan, Ingrid Verbauwhede