We clarify the computational complexity of planarity testing, by showing that planarity testing is hard for L, and lies in SL. This nearly settles the question, since it is widely...
Layout parasitics have great impact on analog circuit performance. This paper presents an algorithm for explicit parasitic control during layout retargeting of analog integrated c...
1 The Ramsey number R(G1, G2) is the smallest integer p such that for any graph G on p vertices2 either G contains G1 or G contains G2, where G denotes the complement of G. In this...
We define a multivariate polynomial that generalizes in a unified way the twovariable interlace polynomial defined by Arratia, Bollob´as and Sorkin on the one hand, and a one-...
Abstract. In this paper we propose an architecture design methodology to optimize the throughput of MD4-based hash algorithms. The proposed methodology includes an iteration bound ...