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VLSID
2004
IEEE
91views VLSI» more  VLSID 2004»
15 years 10 months ago
Program Slicing for ATPG-Based Property Checking
This paper presents a novel technique for abstracting designs in order to increase the efficiency of formal property checking. Bounded Model Checking (BMC), using Satisfiability (...
Vivekananda M. Vedula, Whitney J. Townsend, Jacob ...
TPHOL
2008
IEEE
15 years 4 months ago
Formal Reasoning About Causality Analysis
Systems that can immediately react to their inputs may suffer from cyclic dependencies between their actions and the corresponding trigger conditions. For this reason, causality an...
Jens Brandt, Klaus Schneider
QEST
2007
IEEE
15 years 4 months ago
Stochastic Game Logic
Stochastic game logic (SGL) is a new temporal logic that combines features of alternating temporal logic (to formalize the individual views and cooperation and reaction facilities...
Christel Baier, Tomás Brázdil, Marcu...
FORMATS
2008
Springer
14 years 11 months ago
Some Recent Results in Metric Temporal Logic
Metric Temporal Logic (MTL) is a widely-studied real-time extension of Linear Temporal Logic. In this paper we survey results about the complexity of the satisfiability and model c...
Joël Ouaknine, James Worrell
ICALP
1994
Springer
15 years 2 months ago
On the Cost of Recomputing: Tight Bounds on Pebbling with Faults
We introduce a formal framework to study the time and space complexity of computing with faulty memory. For the fault-free case, time and space complexities were studied using the...
Yonatan Aumann, Judit Bar-Ilan, Uriel Feige