259 search results - page 23 / 52 » Bounded Model Checking for Timed Automata |
ATVA
2004
Springer
15 years 2 months ago
2004
Springer
Timed Bisimulation Preserving Abstraction for Parametric Time-Interval Automata Akio Nakata, Tadaaki Tanimoto, Suguru Sasaki, Teruo Higashino Department of Information Networking, ...
GLVLSI
2006
IEEE
15 years 3 months ago
2006
IEEE
Functional verification is one of the major bottlenecks in microprocessor design. Simulation-based techniques are the most widely used form of processor verification. Efficient ...
DFG
2004
Springer
15 years 1 months ago
2004
Springer
Programmable Logic Controllers (PLC) are widespread in the manufacturing and processing industries to realize sequential procedures and to avoid safety-critical states. For the spe...
MEMOCODE
2006
IEEE
15 years 3 months ago
2006
IEEE
Timed I/O Automata (TIOA) is a mathematical framework for modeling and verification of distributed systems that involve discrete and continuous dynamics. TIOA can be used for exa...
KBSE
2009
IEEE
15 years 4 months ago
2009
IEEE
Propositional bounded model checking has been applied successfully to verify embedded software but is limited by the increasing propositional formula size and the loss of structur...