259 search results - page 24 / 52 » Bounded Model Checking for Timed Automata |
GLVLSI
2009
IEEE
15 years 4 months ago
2009
IEEE
In the context of formal verification Bounded Model Checking (BMC) has shown to be very powerful for large industrial designs. BMC is used to check whether a circuit satisfies a...
78
Voted
FDL
2003
IEEE
15 years 2 months ago
2003
IEEE
Assuring correctness of digital designs is one of the major tasks in the system design flow. Formal methods have been proposed to accompany commonly used simulation approaches. I...
112
Voted
SACMAT
2009
ACM
15 years 4 months ago
2009
ACM
An access control system is often viewed as a state transition system. Given a set of access control policies, a general safety requirement in such a system is to determine whethe...
IPPS
2005
IEEE
15 years 3 months ago
2005
IEEE
— Schedule synthesis based on reachability analysis of timed automata has received attention in the last few years. The main strength of this approach is that the expressiveness ...
107
Voted
ECBS
2010
IEEE
15 years 1 months ago
2010
IEEE
The complexity of software in embedded systems has increased significantly over the last years so that software verification now plays an important role in ensuring the overall pr...