259 search results - page 25 / 52 » Bounded Model Checking for Timed Automata |
85
Voted
ASYNC
2005
IEEE
15 years 3 months ago
2005
IEEE
We propose a novel technique for modeling and verifying timed circuits based on the notion of generalized relative timing. Generalized relative timing constraints can express not ...
64
Voted
TASE
2007
IEEE
15 years 3 months ago
2007
IEEE
Bounded model checking (BMC) based on SAT has been introduced as a complementary method to BDD-based symbolic model checking of LTL and ACTL properties in recent years. For genera...
CORR
2010
Springer
14 years 9 months ago
2010
Springer
Sampled semantics of timed automata is a nite approximation of their dense time behavior. While the former is closer to the actual software or hardware systems ed granularity of ti...
100
Voted
CORR
2010
Springer
14 years 9 months ago
2010
Springer
The transition from single-core to multi-core processors has made multi-threaded software an important subject in computer aided verification. Here, we describe and evaluate an ex...
LFCS
2007
Springer
15 years 3 months ago
2007
Springer
We present a general algorithm scheme for model checking logics of knowledge, common knowledge and linear time, based on simulations to a class of structures that capture the way t...