259 search results - page 48 / 52 » Bounded Model Checking for Timed Automata |
CSL
2009
Springer
15 years 1 months ago
2009
Springer
We introduce tree-width for first order formulae , fotw(). We show that computing fotw is fixed-parameter tractable with parameter fotw. Moreover, we show that on classes of formul...
SEFM
2009
IEEE
15 years 4 months ago
2009
IEEE
Interval temporal logics are based on interval structures over linearly (or partially) ordered domains, where time intervals, rather than time instants, are the primitive ontologi...
TCAD
2010
14 years 4 months ago
2010
Abstract--Functional verification is one of the major bottlenecks in system-on-chip design due to the combined effects of increasing complexity and lack of automated techniques for...
FSTTCS
2009
Springer
15 years 4 months ago
2009
Springer
The paper focuses on the structure of fundamental sequences of ordinals smaller than ε0. A first result is the construction of a monadic second-order formula identifying a given ...
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DAC
2004
ACM
15 years 10 months ago
2004
ACM
Parametric representations used for symbolic simulation of circuits usually use BDDs. After a few steps of symbolic simulation, state set representation is converted from one para...