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ICCAD
2009
IEEE
94views Hardware» more  ICCAD 2009»
14 years 10 months ago
Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint
We propose a layout-driven test-architecture design and optimization technique for core-based system-on-chips (SoCs) that are fabricated using three-dimensional (3D) integration. ...
Li Jiang, Qiang Xu, Krishnendu Chakrabarty, T. M. ...
ICCAD
2009
IEEE
101views Hardware» more  ICCAD 2009»
14 years 10 months ago
Compacting test vector sets via strategic use of implications
As the complexity of integrated circuits has increased, so has the need for improving testing efficiency. Unfortunately, the types of defects are also becoming more complex, which...
Nuno Alves, Jennifer Dworak, R. Iris Bahar, Kundan...
109
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TE
2010
168views more  TE 2010»
14 years 7 months ago
Industry-Oriented Laboratory Development for Mixed-Signal IC Test Education
The semiconductor industry is lacking qualified integrated circuit (IC) test engineers to serve in the field of mixed-signal electronics. The absence of mixed-signal IC test educat...
John Hu, Mark Haffner, Samantha Yoder, Mark Scott,...
123
Voted
FPL
2011
Springer
168views Hardware» more  FPL 2011»
14 years 21 days ago
Scalable Arbiters and Multiplexers for On-FGPA Interconnection Networks
Abstract—Soft on-FGPA interconnection networks are gaining increasing importance since they simplify the integration of heterogeneous components and offer, at the same time, a mo...
Giorgos Dimitrakopoulos, Christoforos Kachris, Emm...
304
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DAC
2012
ACM
13 years 3 months ago
High radix self-arbitrating switch fabric with multiple arbitration schemes and quality of service
A scalable architecture to design high radix switch fabric is presented. It uses circuit techniques to re-use existing input and output data buses and switching logic for fabric c...
Sudhir Satpathy, Reetuparna Das, Ronald G. Dreslin...