1343 search results - page 116 / 269 » Bounded-lifetime integrated circuits |
100
Voted
ICCAD
2001
IEEE
15 years 10 months ago
2001
IEEE
We present a methodology for generating black-box timing models for full-custom transistor-level CMOS circuits. Our approach utilizes transistor-level ternary symbolic timing simu...
93
Voted
ISQED
2006
IEEE
15 years 7 months ago
2006
IEEE
— A methodology is proposed for interdependent setup time and hold time characterization of sequential circuits. Integrating the methodology into an industrial sign-off static ti...
95
Voted
ISPD
2005
ACM
15 years 6 months ago
2005
ACM
In this paper, we summarize circuit placement techniques and algorithms developed by the BLAC CAD research group; these have been integrated into our recursive bisection based pla...
76
Voted
DATE
2010
IEEE
15 years 6 months ago
2010
IEEE
— We propose a methodology for Boolean matching under permutations of inputs and outputs (PP-equivalence checking problem) — a key step in incremental logic design that identif...
APCCAS
2002
IEEE
15 years 6 months ago
2002
IEEE
This paper new two simple PWM (Pulse Width Modulation) signal generations based on modified relaxation oscillator are introduced. Their advantages of the proposed principle are th...