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DATE
2010
IEEE
123views Hardware» more  DATE 2010»
15 years 5 months ago
Interconnect delay and slew metrics using the beta distribution
—Integrated circuit process technology is entering the ultra deep submicron era. At this level, interconnect structure becomes very stiff and the metal resistance shielding effec...
Jun-Kuei Zeng, Chung-Ping Chen
GLVLSI
2010
IEEE
119views VLSI» more  GLVLSI 2010»
15 years 5 months ago
Line width optimization for interdigitated power/ground networks
Higher operating frequencies have increased the importance of inductance in power and ground networks. The effective inductance of the power and ground network can be reduced with...
Renatas Jakushokas, Eby G. Friedman
DATE
2002
IEEE
73views Hardware» more  DATE 2002»
15 years 4 months ago
A Burst-Mode Oriented Back-End for the Balsa Synthesis System
This paper introduces several new component clustering techniques for the optimization of asynchronous systems. In particular, novel “Burst-Mode aware” restrictions are impose...
Tiberiu Chelcea, Steven M. Nowick, Andrew Bardsley...
GLVLSI
2010
IEEE
131views VLSI» more  GLVLSI 2010»
15 years 4 months ago
Clock skew reduction by self-compensating manufacturing variability with on-chip sensors
This paper presents a self-compensation scheme of manufacturing variability for clock skew reduction. In the proposed scheme, a CDN with embedded variability sensors tunes variabl...
Shinya Abe, Kenichi Shinkai, Masanori Hashimoto, T...
DAC
2009
ACM
15 years 4 months ago
Serial reconfigurable mismatch-tolerant clock distribution
We present an unconventional clock distribution that emphasizes flexibility and layout independence. It suits a variety of applications, clock domain shapes and sizes using a modu...
Atanu Chattopadhyay, Zeljko Zilic