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» Bounded-lifetime integrated circuits
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ICCAD
2006
IEEE
127views Hardware» more  ICCAD 2006»
15 years 8 months ago
Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization
Parametric yield loss due to variability can be effectively reduced by both design-time optimization strategies and by adjusting circuit parameters to the realizations of variable...
Murari Mani, Ashish Kumar Singh, Michael Orshansky
ICCAD
2006
IEEE
119views Hardware» more  ICCAD 2006»
15 years 8 months ago
Post-placement voltage island generation
High power consumption will shorten battery life for handheld devices and cause thermal and reliability problems. One way to lower the dynamic power consumption is to reduce the s...
Royce L. S. Ching, Evangeline F. Y. Young, Kevin C...
ISPD
2010
ACM
195views Hardware» more  ISPD 2010»
15 years 6 months ago
Density gradient minimization with coupling-constrained dummy fill for CMP control
In the nanometer IC design, dummy fill is often performed to improve layout pattern uniformity and the post-CMP quality. However, filling dummies might greatly increase intercon...
Huang-Yu Chen, Szu-Jui Chou, Yao-Wen Chang
ICCAD
2008
IEEE
109views Hardware» more  ICCAD 2008»
15 years 6 months ago
Transition-aware decoupling-capacitor allocation in power noise reduction
— Dynamic power noises may not only degrade the circuit performance but also reduce the noise margin which may result in the functional errors in integrated circuit. Decoupling c...
Po-Yuan Chen, Che-Yu Liu, TingTing Hwang
GLVLSI
2006
IEEE
144views VLSI» more  GLVLSI 2006»
15 years 5 months ago
Crosstalk analysis in nanometer technologies
Process variations have become a key concern of circuit designers because of their significant, yet hard to predict impact on performance and signal integrity of VLSI circuits. St...
Shahin Nazarian, Ali Iranli, Massoud Pedram