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» Bounded-lifetime integrated circuits
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ISQED
2005
IEEE
98views Hardware» more  ISQED 2005»
15 years 5 months ago
Wire Planning with Bounded Over-the-Block Wires
Hierarchical approach greatly facilitates large-scale chip design by hiding distracting details in low-level objects. However, the lowlevel designs have to have a global view of h...
Hua Xiang, I-Min Liu, Martin D. F. Wong
ISLPED
2005
ACM
91views Hardware» more  ISLPED 2005»
15 years 5 months ago
LAP: a logic activity packing methodology for leakage power-tolerant FPGAs
As FPGAs enter the nanometer regime, several modifications are needed to reduce the increasing leakage power dissipation. Hence, this work presents some modifications to the FPG...
Hassan Hassan, Mohab Anis, Mohamed I. Elmasry
ISPD
2005
ACM
145views Hardware» more  ISPD 2005»
15 years 5 months ago
NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs
In this paper, we present a hierarchical ratio partitioning based placement algorithm for large-scale mixed-size designs. The placement algorithm consists of three steps: global p...
Tung-Chieh Chen, Tien-Chang Hsu, Zhe-Wei Jiang, Ya...
ISCAS
2003
IEEE
119views Hardware» more  ISCAS 2003»
15 years 5 months ago
Electrical characteristics of multi-layer power distribution grids
Abstract— The design of robust and area efficient power distribution networks for high speed, high complexity integrated circuits has become a challenging task. The integrity of...
Andrey V. Mezhiba, Eby G. Friedman
DAC
2003
ACM
15 years 5 months ago
4G terminals: how are we going to design them?
Fourth-generation wireless communication systems (4G) will have totally different requirements than what front-end designers have been coping with up to now. Designs must be targe...
Jan Craninckx, Stéphane Donnay