This paper presents a new power saving, high speed FPGA design enhancing a previous SiGe CML FPGA based on the Xilinx 6200 FPGA. The design aims at having a higher performance but...
Jong-Ru Guo, Chao You, Kuan Zhou, Bryan S. Goda, R...
This paper describes the early analysis and estimation features currently implemented in the Berkeley Emulation Engine (BEE) system. BEE is an integrated rapid prototyping and des...
Chen Chang, Kimmo Kuusilinna, Brian C. Richards, A...
Design simplification is becoming necessary to respect the target time-to-market of SoCs, and this goal can be obtained by using predesigned IP-cores. However, their correct inte...
In this paper, we propose an effective algorithm flow to handle largescale mixed-size placement. The basic idea is to use floorplanning to guide the placement of objects at the gl...
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...