1343 search results - page 222 / 269 » Bounded-lifetime integrated circuits |
DAC
2003
ACM
16 years 24 days ago
2003
ACM
We present in this paper a multilevel floorplanning/placement framework based on the B*-tree representation, called MB*-tree, to handle the floorplanning and packing for large-sca...
DAC
2004
ACM
16 years 24 days ago
2004
ACM
We present novel and efficient methods for on-line testing in FPGAs. The testing approach uses a ROving TEster (ROTE), which has provable diagnosabilities and is also faster than ...
78
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DAC
2006
ACM
16 years 24 days ago
2006
ACM
As a prevalent constraint, sharp slew rate is often required in circuit design which causes a huge demand for buffering resources. This problem requires ultra-fast buffering techn...
ICCD
2006
IEEE
15 years 8 months ago
2006
IEEE
— As silicon CMOS devices are scaled down into the nanoscale regime, new challenges at both the device and system level are arising. While some of these challenges will be overco...
104
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ISPD
2009
ACM
15 years 6 months ago
2009
ACM
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...