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    » Bounded-lifetime integrated circuits
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    CICC
    2011
    106views more  CICC 2011»
    A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons
    14 years 19 days ago
    A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons
    Download  www.modha.org
    Efforts to achieve the long-standing dream of realizing scalable learning algorithms for networks of spiking neurons in silicon have been hampered by (a) the limited scalability of...
    Jae-sun Seo, Bernard Brezzo, Yong Liu, Benjamin D....
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    SIGMOD
    2012
    ACM
    212views Database» more  SIGMOD 2012»
    Local structure and determinism in probabilistic databases
    13 years 3 months ago
    Local structure and determinism in probabilistic databases
    Download  linqs.cs.umd.edu
    While extensive work has been done on evaluating queries over tuple-independent probabilistic databases, query evaluation over correlated data has received much less attention eve...
    Theodoros Rekatsinas, Amol Deshpande, Lise Getoor
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    GLVLSI
    2006
    IEEE
    112views VLSI» more  GLVLSI 2006»
    A design methodology for temperature variation insensitive low power circuits
    15 years 6 months ago
    A design methodology for temperature variation insensitive low power circuits
    Download  ihome.ust.hk
    Operating an integrated circuit at the prescribed nominal supply voltage is not preferable for reliable circuit operation under temperature fluctuations. A design methodology base...
    Ranjith Kumar, Volkan Kursun
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    IPPS
    2002
    IEEE
    140views Distributed And Parallel Com...» more  IPPS 2002»
    Overview of Hydra: A Concurrent Language for Synchronous Digital Circuit Design
    15 years 5 months ago
    Overview of Hydra: A Concurrent Language for Synchronous Digital Circuit Design
    Download  www.dcs.gla.ac.uk
    Hydra is a computer hardware description language that integrates several kinds of software tool (simulation, netlist generation and timing analysis) within a single circuit speci...
    John O'Donnell
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    ISCAS
    2006
    IEEE
    86views Hardware» more  ISCAS 2006»
    Fast timing analysis of plane circuits via two-layer CNN-based modeling
    15 years 6 months ago
    Fast timing analysis of plane circuits via two-layer CNN-based modeling
    Download  nlab.ee.tokushima-u.ac.jp
    Abstract— A fast timing analysis of plane circuits via two-layer CNNbased modeling, which is necessary for the solution of power/signal integrity problems in printed circuit boar...
    Yuichi Tanji, Hideki Asai, Masayoshi Oda, Yoshifum...
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