Sciweavers

1343 search results - page 62 / 269
» Bounded-lifetime integrated circuits
Sort
View
INTEGRATION
2006
102views more  INTEGRATION 2006»
14 years 9 months ago
A parameterized graph-based framework for high-level test synthesis
Improving testability during the early stages of high-level synthesis has several benefits including reduced test hardware overheads, reduced test costs, reduced design iterations...
Saeed Safari, Amir-Hossein Jahangir, Hadi Esmaeilz...
DATE
2002
IEEE
151views Hardware» more  DATE 2002»
15 years 2 months ago
Analog Circuit Sizing Using Adaptive Worst-Case Parameter Sets
In this paper, a method for nominal design of analog integrated circuits is presented that includes process variations and operating ranges by worst-case parameter sets. These set...
Robert Schwencker, Frank Schenkel, Michael Pronath...
VTS
2000
IEEE
97views Hardware» more  VTS 2000»
15 years 2 months ago
A Low-Speed BIST Framework for High-Performance Circuit Testing
Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to...
Hans G. Kerkhoff, Mansour Shashaani, Manoj Sachdev
DAC
2007
ACM
15 years 10 months ago
Placement of 3D ICs with Thermal and Interlayer Via Considerations
Thermal problems and limitations on interlayer via densities are important design constraints on three-dimensional integrated circuits (3D ICs), and need to be considered during g...
Brent Goplen, Sachin S. Sapatnekar
DAC
1999
ACM
15 years 2 months ago
Interconnect Analysis: From 3-D Structures to Circuit Models
In this survey paper we describethe combination of: discretized integral formulations, sparsication techniques, and krylov-subspace based model-order reduction that has led to rob...
Mattan Kamon, Nuno Alexandre Marques, Yehia Massou...