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» Bounded-lifetime integrated circuits
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FPGA
2003
ACM
154views FPGA» more  FPGA 2003»
15 years 3 months ago
Parallel placement for field-programmable gate arrays
Placement and routing are the most time-consuming processes in automatically synthesizing and configuring circuits for field-programmable gate arrays (FPGAs). In this paper, we ...
Pak K. Chan, Martine D. F. Schlag
EH
2000
IEEE
81views Hardware» more  EH 2000»
15 years 2 months ago
Toward Self-Repairing and Self-Replicating Hardware: The Embryonics Approach
The growth and operation of all living beings are directed by the interpretation, in each of their cells, of a chemical program, the DNA string or genome. This process is the sour...
Daniel Mange, Moshe Sipper, André Stauffer,...
ICCAD
1994
IEEE
91views Hardware» more  ICCAD 1994»
15 years 2 months ago
A loosely coupled parallel algorithm for standard cell placement
We present a loosely coupled parallel algorithm for the placement of standard cell integrated circuits. Our algorithm is a derivative of simulated annealing. The implementation of...
Wern-Jieh Sun, Carl Sechen
DAC
2010
ACM
15 years 1 months ago
Representative path selection for post-silicon timing prediction under variability
The identification of speedpaths is required for post-silicon (PS) timing validation, and it is currently becoming timeconsuming due to manufacturing variations. In this paper we...
Lin Xie, Azadeh Davoodi
DATE
2009
IEEE
88views Hardware» more  DATE 2009»
15 years 1 months ago
A generic framework for scan capture power reduction in fixed-length symbol-based test compression environment
Growing test data volume and overtesting caused by excessive scan capture power are two of the major concerns for the industry when testing large integrated circuits. Various test...
Xiao Liu, Qiang Xu