1343 search results - page 90 / 269 » Bounded-lifetime integrated circuits |
GLVLSI
2007
IEEE
15 years 1 months ago
2007
IEEE
This paper describes a formal verification methodology of highnthesis (HLS) process. The abstraction level of the input to HLS is so high compared to that of the output that the v...
ASYNC
2004
IEEE
15 years 1 months ago
2004
IEEE
As integrated circuit technologies get smaller, circuit and architectural trends make transmitting data across long on-chip wires increasingly important yet increasingly expensive...
CASES
2006
ACM
15 years 1 months ago
2006
ACM
We present a new technique for compiling run-time reconfigurable hardware designs. Run-time reconfigurable embedded systems can deliver promising benefits over implementations in ...
ICCAD
1991
IEEE
15 years 1 months ago
1991
IEEE
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...
ASPDAC
2007
ACM
14 years 11 months ago
2007
ACM
Rising interconnect delay and power consumption have motivated the investigation of alternative integrated circuit routing architectures. In particular, the X Architecture, which ...