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» Bounding Loop Iterations for Timing Analysis
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AAAI
2012
12 years 12 months ago
Generalized Sampling and Variance in Counterfactual Regret Minimization
In large extensive form games with imperfect information, Counterfactual Regret Minimization (CFR) is a popular, iterative algorithm for computing approximate Nash equilibria. Whi...
Richard G. Gibson, Marc Lanctot, Neil Burch, Duane...
167
Voted
CORR
2012
Springer
286views Education» more  CORR 2012»
13 years 5 months ago
A Faster Algorithm for Solving One-Clock Priced Timed Games
One-clock priced timed games is a class of two-player, zero-sum, continuous-time games that was defined and thoroughly studied in previous works. We show that One-clock priced ti...
Thomas Dueholm Hansen, Rasmus Ibsen-Jensen, Peter ...
ISPD
1998
ACM
89views Hardware» more  ISPD 1998»
15 years 1 months ago
Filling and slotting: analysis and algorithms
In very deep-submicron VLSI, certain manufacturing steps – notably optical exposure, resist development and etch, chemical vapor deposition and chemical-mechanical polishing (CM...
Andrew B. Kahng, Gabriel Robins, Anish Singh, Huij...
STOC
2007
ACM
239views Algorithms» more  STOC 2007»
15 years 9 months ago
Approximating minimum bounded degree spanning trees to within one of optimal
In the MINIMUM BOUNDED DEGREE SPANNING TREE problem, we are given an undirected graph with a degree upper bound Bv on each vertex v, and the task is to find a spanning tree of min...
Mohit Singh, Lap Chi Lau
DATE
2009
IEEE
90views Hardware» more  DATE 2009»
15 years 4 months ago
Property analysis and design understanding
—Verification is a major issue in circuit and system design. Formal methods like bounded model checking (BMC) can guarantee a high quality of the verification. There are severa...
Ulrich Kühne, Daniel Große, Rolf Drechs...