23 search results - page 5 / 5 » Bounding Worst-Case Instruction Cache Performance |
73
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SIGMETRICS
1997
ACM
15 years 1 months ago
1997
ACM
In this paper we present a performance study of memory reference behavior in network protocol processing, using an Internet-based protocol stack implemented in the x-kernel runnin...
104
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VLDB
1999
ACM
15 years 1 months ago
1999
ACM
Recent high-performance processors employ sophisticated techniques to overlap and simultaneously execute multiple computation and memory operations. Intuitively, these techniques ...
84
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CGO
2006
IEEE
15 years 1 months ago
2006
IEEE
Modern computer systems are called on to deal with billions of events every second, whether they are instructions executed, memory locations accessed, or packets forwarded. This p...