109 search results - page 17 / 22 » Bounds on Memory Bandwidth in Streamed Computations |
119
click to vote
FCCM
1997
IEEE
15 years 6 months ago
1997
IEEE
We propose an FPGA chip architecture based on a conventional FPGA logic array core, in which I/O pins are clocked at a much higher rate than that of the logic array that they serv...
103
Voted
LCPC
2007
Springer
15 years 8 months ago
2007
Springer
This paper describes the implementation of a runtime library for asynchronous communication in the Cell BE processor. The runtime library implementation provides with several servi...
117
click to vote
NSDI
2004
15 years 3 months ago
2004
This paper describes the design, implementation, and experimental evaluation of OverQoS, an overlay-based architecture for enhancing the best-effort service of today's Intern...
110
Voted
ANCS
2009
ACM
14 years 11 months ago
2009
ACM
In this paper we introduce the Range Trie, a new multiway tree data structure for address lookup. Each Range Trie node maps to an address range [Na, Nb) and performs multiple comp...
127
click to vote
INFOCOM
2007
IEEE
15 years 8 months ago
2007
IEEE
— The need for efficient counter architecture has arisen for the following two reasons. Firstly, a number of data streaming algorithms and network management applications requir...