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ICCD
2006
IEEE
103views Hardware» more  ICCD 2006»
15 years 6 months ago
Architectural Support for Run-Time Validation of Control Flow Transfer
—Current micro-architecture blindly uses the address in the program counter to fetch and execute instructions without validating its legitimacy. Whenever this blind-folded instru...
Yixin Shi, Sean Dempsey, Gyungho Lee
IEEEPACT
2000
IEEE
15 years 2 months ago
The Effect of Code Reordering on Branch Prediction
Branch prediction accuracy is a very important factor for superscalarprocessor performance. The ability topredict the outcome of a branch allows the processor to effectively use a...
Alex Ramírez, Josep-Lluis Larriba-Pey, Mate...
ARCS
2010
Springer
15 years 2 months ago
Complexity-Effective Rename Table Design for Rapid Speculation Recovery
Register renaming is a widely used technique to remove false data dependencies in contemporary superscalar microprocessors. The register rename logic includes a mapping table that ...
Görkem Asilioglu, Emine Merve Kaya, Oguz Ergi...
PODS
2002
ACM
168views Database» more  PODS 2002»
15 years 9 months ago
Conjunctive Selection Conditions in Main Memory
We consider the fundamental operation of applying a conjunction of selection conditions to a set of records. With large main memories available cheaply, systems may choose to keep...
Kenneth A. Ross
78
Voted
MICRO
1999
IEEE
115views Hardware» more  MICRO 1999»
15 years 2 months ago
Fetch Directed Instruction Prefetching
Instruction supply is a crucial component of processor performance. Instruction prefetching has been proposed as a mechanism to help reduce instruction cache misses, which in turn...
Glenn Reinman, Brad Calder, Todd M. Austin