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ISPASS
2006
IEEE
15 years 3 months ago
Branch trace compression for snapshot-based simulation
We present a scheme to compress branch trace information for use in snapshot-based microarchitecture simulation. The compressed trace can be used to warm any arbitrary branch pred...
Kenneth C. Barr, Krste Asanovic
ICCD
2002
IEEE
110views Hardware» more  ICCD 2002»
15 years 6 months ago
Branch Predictor Prediction: A Power-Aware Branch Predictor for High-Performance Processors
We introduce Branch Predictor Prediction (BPP) as a power-aware branch prediction technique for high performance processors. Our predictor reduces branch prediction power dissipat...
Amirali Baniasadi, Andreas Moshovos
HPCA
2007
IEEE
15 years 10 months ago
Improving Branch Prediction and Predicated Execution in Out-of-Order Processors
If-conversion is a compiler technique that reduces the misprediction penalties caused by hard-to-predict branches, transforming control dependencies into data dependencies. Althou...
Eduardo Quiñones, Joan-Manuel Parcerisa, An...
87
Voted
ISCA
1995
IEEE
121views Hardware» more  ISCA 1995»
15 years 1 months ago
A Comparative Analysis of Schemes for Correlated Branch Prediction
Modern high-performance architectures require extremely accurate branch prediction to overcome the performance limitations of conditional branches. We present a framework that cat...
Cliff Young, Nicholas C. Gloy, Michael D. Smith
66
Voted
HPCA
2008
IEEE
15 years 10 months ago
Address-branch correlation: A novel locality for long-latency hard-to-predict branches
Hard-to-predict branches depending on longlatency cache-misses have been recognized as a major performance obstacle for modern microprocessors. With the widening speed gap between...
Hongliang Gao, Yi Ma, Martin Dimitrov, Huiyang Zho...