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» Broadcast scheduling: algorithms and complexity
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81
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ASPDAC
2006
ACM
178views Hardware» more  ASPDAC 2006»
15 years 4 months ago
Hardware architecture design of an H.264/AVC video codec
Abstract—H.264/AVC is the latest video coding standard. It significantly outperforms the previous video coding standards, but the extraordinary huge computation complexity and m...
Tung-Chien Chen, Chung-Jr Lian, Liang-Gee Chen
92
Voted
EGH
2005
Springer
15 years 3 months ago
Optimal automatic multi-pass shader partitioning by dynamic programming
Complex shaders must be partitioned into multiple passes to execute on GPUs with limited hardware resources. Automatic partitioning gives rise to an NP-hard scheduling problem tha...
Alan Heirich
97
Voted
DATE
1999
IEEE
147views Hardware» more  DATE 1999»
15 years 2 months ago
Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
Nicola Nicolici, Bashir M. Al-Hashimi
CN
2006
161views more  CN 2006»
14 years 10 months ago
A multimedia traffic modeling framework for simulation-based performance evaluation studies
The emergence of high-speed communication systems has enabled the support of complex multimedia applications. The traffic patterns generated by such applications are likely to be ...
Assen Golaup, Hamid Aghvami
MICRO
2010
IEEE
202views Hardware» more  MICRO 2010»
14 years 5 months ago
Hardware Support for Relaxed Concurrency Control in Transactional Memory
Today's transactional memory systems implement the two-phase-locking (2PL) algorithm which aborts transactions every time a conflict happens. 2PL is a simple algorithm that pr...
Utku Aydonat, Tarek S. Abdelrahman