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» Broadcast scheduling: algorithms and complexity
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TVLSI
2008
120views more  TVLSI 2008»
14 years 10 months ago
An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors
Much effort in register transfer level (RTL) design has been devoted to developing "push-button" types of tools. However, given the highly complex nature, and lack of con...
Dongwan Shin, Andreas Gerstlauer, Rainer Döme...
CCE
2004
14 years 10 months ago
Optimization under uncertainty: state-of-the-art and opportunities
A large number of problems in production planning and scheduling, location, transportation, finance, and engineering design require that decisions be made in the presence of uncer...
Nikolaos V. Sahinidis
ORL
2000
77views more  ORL 2000»
14 years 10 months ago
Improved dynamic programs for some batching problems involving the maximum lateness criterion
We study four scheduling problems involving the maximum lateness criterion and an element of batching. For all the problems that we examine, algorithms appear in the literature th...
Albert P. M. Wagelmans, A. E. Gerodimos
TVLSI
2002
102views more  TVLSI 2002»
14 years 9 months ago
Low-power data forwarding for VLIW embedded architectures
In this paper, we propose a low-power approach to the design of embedded very long instruction word (VLIW) processor architectures based on the forwarding (or bypassing) hardware, ...
Mariagiovanna Sami, Donatella Sciuto, Cristina Sil...
IEEEPACT
2009
IEEE
14 years 7 months ago
ITCA: Inter-task Conflict-Aware CPU Accounting for CMPs
Abstract--Chip-MultiProcessor (CMP) architectures are becoming more and more popular as an alternative to the traditional processors that only extract instruction-level parallelism...
Carlos Luque, Miquel Moretó, Francisco J. C...