Sciweavers

577 search results - page 32 / 116
» Budget Feasible Mechanisms
Sort
View
MICRO
2007
IEEE
120views Hardware» more  MICRO 2007»
15 years 6 months ago
Scavenger: A New Last Level Cache Architecture with Global Block Priority
Addresses suffering from cache misses typically exhibit repetitive patterns due to the temporal locality inherent in the access stream. However, we observe that the number of inte...
Arkaprava Basu, Nevin Kirman, Meyrem Kirman, Maina...
DATE
2003
IEEE
94views Hardware» more  DATE 2003»
15 years 5 months ago
Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors
Modern embedded processors use data caches with higher and higher degrees of associativity in order to increase performance. A set–associative data cache consumes a significant...
Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru...
DSN
2003
IEEE
15 years 5 months ago
ICR: In-Cache Replication for Enhancing Data Cache Reliability
Processor caches already play a critical role in the performance of today’s computer systems. At the same time, the data integrity of words coming out of the caches can have ser...
Wei Zhang 0002, Sudhanva Gurumurthi, Mahmut T. Kan...
ICMI
2003
Springer
160views Biometrics» more  ICMI 2003»
15 years 5 months ago
Sensitivity to haptic-audio asynchrony
The natural role of sound in actions involving mechanical impact and vibration suggests the use of auditory display as an augmentation to virtual haptic interfaces. In order to bu...
Bernard D. Adelstein, Durand R. Begault, Mark R. A...
MICRO
2002
IEEE
128views Hardware» more  MICRO 2002»
15 years 4 months ago
Compiler-directed instruction cache leakage optimization
Excessive power consumption is widely considered as a major impediment to designing future microprocessors. With the continued scaling down of threshold voltages, the power consum...
Wei Zhang 0002, Jie S. Hu, Vijay Degalahal, Mahmut...