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IEEEPACT
2006
IEEE
15 years 4 months ago
Core architecture optimization for heterogeneous chip multiprocessors
Previous studies have demonstrated the advantages of single-ISA heterogeneous multi-core architectures for power and performance. However, none of those studies examined how to de...
Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi
FPL
2003
Springer
95views Hardware» more  FPL 2003»
15 years 3 months ago
A Model for Hardware Realization of Kernel Loops
Abstract. Hardware realization of kernel loops holds the promise of accelerating the overall application performance and is therefore an important part of the synthesis process. In...
Jirong Liao, Weng-Fai Wong, Tulika Mitra
CODES
2002
IEEE
15 years 2 months ago
Compiler-directed customization of ASIP cores
This paper presents an automatic method to customize embedded application-specific instruction processors (ASIPs) based on compiler analysis. ASIPs, also known as embedded soft c...
T. Vinod Kumar Gupta, Roberto E. Ko, Rajeev Barua
VMV
2003
146views Visualization» more  VMV 2003»
14 years 11 months ago
ADB-Trees: Controlling the Error of Time-Critical Collision Detection
We present a novel framework for hierarchical collision detection that can be applied to virtually all bounding volume (BV) hierarchies. It allows an application to trade quality ...
Jan Klein, Gabriel Zachmann
JSAC
2007
147views more  JSAC 2007»
14 years 9 months ago
Cross-Layer Optimization for Video Summary Transmission over Wireless Networks
Abstract— Video summarization has gained increased popularity in the emerging multimedia communication applications, however, very limited work has been conducted to address the ...
Dalei Wu, Song Ci, Haohong Wang