30 search results - page 2 / 6 » Buffer Insertion with Accurate Gate and Interconnect Delay C... |
ASPDAC
2004
ACM
15 years 2 months ago
2004
ACM
As gate delays decrease faster than wire delays for each technology generation, buffer insertion becomes a popular method to reduce the interconnect delay. Several modern buffer in...
VLSID
2003
IEEE
15 years 10 months ago
2003
IEEE
We consider the problem of minimizing the delay in transporting a signal across a distance in a VLSI circuit.The problem can be restated as a combined buffer insertion, buffer siz...
VLSID
1999
IEEE
15 years 1 months ago
1999
IEEE
Recently Lillis, et al. presented an elegant dynamic programming approach to RC interconnect delay optimization through driver sizing, repeater insertion, and, wire sizing which e...
ICCD
2005
IEEE
15 years 3 months ago
2005
IEEE
— In this work we investigate the buffer insertion problem under process variations. Sub 100-nm fabrication process causes significant variations on many design parameters. We p...
VLSISP
2008
14 years 9 months ago
2008
Each new semiconductor technology node brings smaller, faster transistors and smaller, slower wires. In particular, long interconnect wires in modern FPGAs now require rebuffering ...