30 search results - page 3 / 6 » Buffer Insertion with Accurate Gate and Interconnect Delay C... |
DAC
1998
ACM
15 years 1 months ago
1998
ACM
Interconnect-driven optimization is an increasingly important step in high-performance design. Algorithms for buffer insertion have been successfully utilized to reduce delay in gl...
DAC
2008
ACM
15 years 10 months ago
2008
ACM
Due to skewed scaling of interconnect delay and cell delay with technology scaling, modern VLSI timing closure requires use of extensive buffer insertion. Inserting a large number...
ISCAS
1999
IEEE
15 years 1 months ago
1999
IEEE
- A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range o...
DAC
2009
ACM
15 years 10 months ago
2009
ACM
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...
69
Voted
ICCAD
2003
IEEE
15 years 6 months ago
2003
IEEE
In this paper, we study the problem of retiming of sequential circuits with both interconnect and gate delay. Most retiming algorithms have assumed ideal conditions for the non-lo...