30 search results - page 6 / 6 » Buffer Insertion with Accurate Gate and Interconnect Delay C... |
81
Voted
ISPD
2003
ACM
15 years 2 months ago
2003
ACM
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
ISPD
1998
ACM
15 years 1 months ago
1998
ACM
We describe a novel iterationless approach for computing the effective capacitance of an interconnect load at a driving gate output. Our new approach is considerably faster than p...
ICCD
2004
IEEE
15 years 6 months ago
2004
IEEE
This paper describes XTalkDelay, an industrial-strength methodology and tool for measuring the impact of crosstalk on delays of paths in a design. The main cornerstone of XTalkDel...
107
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GLVLSI
2006
IEEE
15 years 3 months ago
2006
IEEE
Process technology and environment-induced variability of gates and wires in VLSI circuits make timing analyses of such circuits a challenging task. Process variation can have a s...
78
Voted
INTEGRATION
2006
14 years 9 months ago
2006
In the context of physical synthesis, large-scale standard-cell placement algorithms must facilitate incremental changes to layout, both local and global. In particular, flexible ...