113 search results - page 14 / 23 » Buffer and register allocation for memory space optimization |
IEEEPACT
2009
IEEE
15 years 6 months ago
2009
IEEE
Abstract—Load elimination is a classical compiler transformation that is increasing in importance for multi-core and many-core architectures. The effect of the transformation is ...
112
Voted
ICCD
1999
IEEE
15 years 4 months ago
1999
IEEE
This research explores any potential for an on-chip cache compression which can reduce not only cache miss ratio but also miss penalty, if main memory is also managed in compresse...
122
click to vote
CASES
2007
ACM
15 years 3 months ago
2007
ACM
Dynamic binary translation (DBT) has been used to achieve numerous goals (e.g., better performance) for general-purpose computers. Recently, DBT has also attracted attention for e...
85
Voted
WADS
2007
Springer
15 years 5 months ago
2007
Springer
In the faulty-memory RAM model, the content of memory cells can get corrupted at any time during the execution of an algorithm, and a constant number of uncorruptible registers are...
OOPSLA
2004
Springer
15 years 5 months ago
2004
Springer
This paper introduces dynamic object colocation, an optimization to reduce copying costs in generational and other incremental garbage collectors by allocating connected objects t...