113 search results - page 15 / 23 » Buffer and register allocation for memory space optimization |
111
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CODES
2008
IEEE
15 years 6 months ago
2008
IEEE
Software-controlled scratchpad memory is increasingly employed in embedded systems as it offers better timing predictability compared to caches. Previous scratchpad allocation alg...
VLSISP
2008
14 years 11 months ago
2008
This paper describes a novel memory hierarchy and line-pixel-lookahead (LPL) for an H.264/AVC video decoder. The memory system is the bottleneck of most video processors, particula...
163
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POPL
2002
ACM
15 years 12 months ago
2002
ACM
Data-layout optimizations rearrange fields within objects, objects within objects, and objects within the heap, with the goal of increasing spatial locality. While the importance ...
105
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EUROPAR
2009
Springer
15 years 3 months ago
2009
Springer
The Cell Broadband Engine (Cell BE) is a heterogeneous multi-core processor specifically designed to exploit thread-level parallelism. Its memory model comprehends a common shared ...
113
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CASES
2006
ACM
15 years 5 months ago
2006
ACM
Multiprocessor system-on-chip (MPSoC) is an integrated circuit containing multiple instruction-set processors on a single chip that implements most of the functionality of a compl...