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» Buffer and register allocation for memory space optimization
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FPGA
2010
ACM
232views FPGA» more  FPGA 2010»
14 years 9 months ago
High-throughput bayesian computing machine with reconfigurable hardware
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
Mingjie Lin, Ilia Lebedev, John Wawrzynek
INFOCOM
2007
IEEE
15 years 3 months ago
Statistical Multiplexing Over DSL Networks
— Most previous work in statistical multiplexing only considered the case where the link transmission rates are fixed. In this paper, we consider statistical multiplexing in net...
Jianwei Huang, Chee-Wei Tan, Mung Chiang, Raphael ...
65
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PE
2006
Springer
79views Optimization» more  PE 2006»
14 years 9 months ago
Parallel downloads for streaming applications - a resequencing analysis
Several recent studies have proposed methods to accelerate the receipt of a file by downloading its parts from different servers in parallel. The schemes suggested in most propose...
Yoav Nebat, Moshe Sidi
EUROPAR
2010
Springer
14 years 9 months ago
Power-Efficient Spilling Techniques for Chip Multiprocessors
Abstract. Current trends in CMPs indicate that the core count will increase in the near future. One of the main performance limiters of these forthcoming microarchitectures is the ...
Enric Herrero, José González, Ramon ...
IWMM
2010
Springer
173views Hardware» more  IWMM 2010»
15 years 2 months ago
CETS: compiler enforced temporal safety for C
Temporal memory safety errors, such as dangling pointer dereferences and double frees, are a prevalent source of software bugs in unmanaged languages such as C. Existing schemes t...
Santosh Nagarakatte, Jianzhou Zhao, Milo M. K. Mar...