113 search results - page 7 / 23 » Buffer and register allocation for memory space optimization |
INFOCOM
1994
IEEE
15 years 3 months ago
1994
IEEE
This paper is motivated by the need to support multiple service classes in fast packet-switched networks. We address the problem of characterizing and designing scheduling policie...
SAC
2004
ACM
15 years 5 months ago
2004
ACM
Clustered L0 buffers are an interesting alternative to reduce energy consumption in the instruction memory hierarchy of embedded VLIW processors. Currently, the synthesis of L0 cl...
CGO
2007
IEEE
15 years 6 months ago
2007
IEEE
Memory transfers are becoming more important to optimize, for both performance and power consumption. With this goal in mind, new register allocation schemes are developed, which ...
111
click to vote
IPPS
2006
IEEE
15 years 5 months ago
2006
IEEE
In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architect...
113
click to vote
LCTRTS
2005
Springer
15 years 5 months ago
2005
Springer
Effective use of the memory hierarchy is critical for achieving high performance on embedded systems. We focus on the class of streaming applications, which is increasingly preval...