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» Buffer minimization using max-coloring
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DATE
2000
IEEE
94views Hardware» more  DATE 2000»
15 years 2 months ago
Shared Memory Implementations of Synchronous Dataflow Specifications
There has been a proliferation of block-diagram environments for specifying and prototyping DSP systems. These include tools from academia like Ptolemy [3], and GRAPE [7], and com...
Praveen K. Murthy, Shuvra S. Bhattacharyya
ASPDAC
2008
ACM
129views Hardware» more  ASPDAC 2008»
14 years 11 months ago
Clock tree synthesis with data-path sensitivity matching
This paper investigates methods for minimizing the impact of process variation on clock skew using buffer and wire sizing. While most papers on clock trees ignore data-path circuit...
Matthew R. Guthaus, Dennis Sylvester, Richard B. B...
ISCC
2007
IEEE
141views Communications» more  ISCC 2007»
15 years 3 months ago
Switch Architectures For Small-buffered Optical Packet Switched Networks
One of the difficulties of optical packet switched networks is buffering optical packets in the network. Currently, one solution that can be used for buffering in the optical dom...
Onur Alparslan, Shin'ichi Arakawa, Masayuki Murata
90
Voted
ISLPED
2007
ACM
138views Hardware» more  ISLPED 2007»
14 years 11 months ago
Power optimal MTCMOS repeater insertion for global buses
This paper addresses the problem of power-optimal repeater insertion for global buses in the presence of crosstalk noise. MTCMOS technique by inserting high-Vth sleep transistors ...
Hanif Fatemi, Behnam Amelifard, Massoud Pedram
MICRO
2010
IEEE
130views Hardware» more  MICRO 2010»
14 years 7 months ago
Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks
As the number of cores on a single chip increases with more recent technologies, a packet-switched on-chip interconnection network has become a de facto communication paradigm for ...
Minseon Ahn, Eun Jung Kim