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» Buffer minimization using max-coloring
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ASPDAC
2000
ACM
104views Hardware» more  ASPDAC 2000»
15 years 1 months ago
Design of digital neural cell scheduler for intelligent IB-ATM switch
— We present the architecture of the ATM banyan switch composed of pattern process and high-speed digital neural cell scheduler. An input buffer type ATM switch with a window-bas...
J.-K. Lee, Seung-Min Lee, Mike Myung-Ok Lee, D.-W....
EUROPAR
2005
Springer
15 years 3 months ago
Cost / Performance Trade-Offs and Fairness Evaluation of Queue Mapping Policies
Whereas the established interconnection networks (ICTN) achieve low latency by operating in the linear region, i.e. oversizing the fabric, the recent strict cost and power constrai...
Teresa Nachiondo Frinós, Jose Flich, Jos&ea...
ISCA
2008
IEEE
170views Hardware» more  ISCA 2008»
15 years 4 months ago
Polymorphic On-Chip Networks
As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. We beg...
Martha Mercaldi Kim, John D. Davis, Mark Oskin, To...
ISCC
2007
IEEE
164views Communications» more  ISCC 2007»
15 years 3 months ago
DTSN: Distributed Transport for Sensor Networks
: This paper presents the Distributed Transport for Sensor Networks (DTSN), a novel reliable transport protocol for convergecast and unicast communications in Wireless Sensor Netwo...
Bruno Marchi, António Grilo, Mário S...
SSDBM
2007
IEEE
116views Database» more  SSDBM 2007»
15 years 3 months ago
A Distributed Algorithm for Joins in Sensor Networks
Given their autonomy, flexibility and large range of functionality, wireless sensor networks can be used as an effective and discrete means for monitoring data in many domains. T...
Alexandru Coman, Mario A. Nascimento