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VLSID
2003
IEEE
183views VLSI» more  VLSID 2003»
14 years 6 months ago
Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy
We consider the problem of minimizing the delay in transporting a signal across a distance in a VLSI circuit.The problem can be restated as a combined buffer insertion, buffer siz...
Vani Prasad, Madhav P. Desai
ISSS
1999
IEEE
149views Hardware» more  ISSS 1999»
13 years 10 months ago
A Buffer Merging Technique for Reducing Memory Requirements of Synchronous Dataflow Specifications
Synchronous Dataflow, a subset of dataflow, has proven to be a good match for specifying DSP programs. Because of the limited amount of memory in embedded DSPs, a key problem duri...
Praveen K. Murthy, Shuvra S. Bhattacharyya
ASPDAC
1995
ACM
106views Hardware» more  ASPDAC 1995»
13 years 9 months ago
Performance driven multiple-source bus synthesis using buffer insertion
A heuristic algorithm for a given topology of a multiple-source and multiple-sink bus to reduce the signal delay time is proposed. The algorithm minimizes the delay by inserting bu...
Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng, Ting-...
ISPD
1997
ACM
68views Hardware» more  ISPD 1997»
13 years 10 months ago
Closed form solution to simultaneous buffer insertion/sizing and wire sizing
In this paper, we consider the delay minimization problem of a wire by simultaneously considering bu er insertion, bu er sizing and wire sizing. We consider three versions of the ...
Chris C. N. Chu, D. F. Wong
VL
1995
IEEE
121views Visual Languages» more  VL 1995»
13 years 9 months ago
Buffering of Intermediate Results in Dataflow Diagrams
Buffering of intermediate results in dataflow diagrams can significantly reduce latency when a user browses these results or re-executes a diagram with slightly different inputs. ...
Allison Woodruff, Michael Stonebraker