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GRAPHICSINTERFACE
2004
14 years 11 months ago
Compressed Multisampling for Efficient Hardware Edge Antialiasing
Today's hardware graphics accelerators incorporate techniques to antialias edges and minimize geometry-related sampling artifacts. Two such techniques, brute force supersampl...
Philippe Beaudoin, Pierre Poulin
DAC
2006
ACM
15 years 10 months ago
Exploring trade-offs in buffer requirements and throughput constraints for synchronous dataflow graphs
Multimedia applications usually have throughput constraints. An implementation must meet these constraints, while it minimizes resource usage and energy consumption. The compute i...
Sander Stuijk, Marc Geilen, Twan Basten
ISLPED
2006
ACM
122views Hardware» more  ISLPED 2006»
15 years 3 months ago
Dynamic thermal clock skew compensation using tunable delay buffers
—The thermal gradients existing in high-performance circuits may significantly affect their timing behavior, in particular, by increasing the skew of the clock net and/or alteri...
Ashutosh Chakraborty, Karthik Duraisami, Ashoka Vi...
GLOBECOM
2007
IEEE
15 years 1 months ago
Efficient Scheduling for Heterogeneous Services in OFDMA Downlink
We consider optimal allocation of resources to users in a downlink OFDMA system to support heterogeneous applications consisting of both deadline-sensitive (DS) and best-effort (BE...
Rajiv Agarwal, Vinay R. Majjigi, Rath Vannithamby,...
CASES
2007
ACM
15 years 1 months ago
Fragment cache management for dynamic binary translators in embedded systems with scratchpad
Dynamic binary translation (DBT) has been used to achieve numerous goals (e.g., better performance) for general-purpose computers. Recently, DBT has also attracted attention for e...
José Baiocchi, Bruce R. Childers, Jack W. D...