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FCCM
2009
IEEE
115views VLSI» more  FCCM 2009»
13 years 10 months ago
Multi-Core Architecture on FPGA for Large Dictionary String Matching
FPGA has long been considered an attractive platform for high performance implementations of string matching. However, as the size of pattern dictionaries continues to grow, such ...
Qingbo Wang, Viktor K. Prasanna
ALGORITHMICA
2005
84views more  ALGORITHMICA 2005»
13 years 6 months ago
Optimal Read-Once Parallel Disk Scheduling
An optimal prefetching and I/O scheduling algorithm L-OPT, for parallel I/O systems, using a read-once model of block references is presented. The algorithm uses knowledge of the n...
Mahesh Kallahalla, Peter J. Varman
ASPDAC
2008
ACM
129views Hardware» more  ASPDAC 2008»
13 years 8 months ago
Clock tree synthesis with data-path sensitivity matching
This paper investigates methods for minimizing the impact of process variation on clock skew using buffer and wire sizing. While most papers on clock trees ignore data-path circuit...
Matthew R. Guthaus, Dennis Sylvester, Richard B. B...
VLSID
2007
IEEE
130views VLSI» more  VLSID 2007»
14 years 6 months ago
Memory Architecture Exploration for Power-Efficient 2D-Discrete Wavelet Transform
The Discrete Wavelet Transform (DWT) forms the core of the JPEG2000 image compression algorithm. Since the JPEG2000 compression application is heavily data-intensive, the overall ...
Rahul Jain, Preeti Ranjan Panda
SIGMOD
2008
ACM
145views Database» more  SIGMOD 2008»
14 years 6 months ago
Optimizing complex queries with multiple relation instances
Today's query processing engines do not take advantage of the multiple occurrences of a relation in a query to improve performance. Instead, each instance is treated as a dis...
Yu Cao, Gopal C. Das, Chee Yong Chan, Kian-Lee Tan