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111
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LCTRTS
2007
Springer
15 years 7 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...
104
Voted
OSDI
2004
ACM
16 years 1 months ago
Program-Counter-Based Pattern Classification in Buffer Caching
Program-counter-based (PC-based) prediction techniques have been shown to be highly effective and are widely used in computer architecture design. In this paper, we explore the op...
Chris Gniady, Ali Raza Butt, Y. Charlie Hu
85
Voted
ISLPED
2003
ACM
91views Hardware» more  ISLPED 2003»
15 years 6 months ago
Reducing reorder buffer complexity through selective operand caching
Modern superscalar processors implement precise interrupts by using the Reorder Buffer (ROB). In some microarchitectures , such as the Intel P6, the ROB also serves as a repositor...
Gurhan Kucuk, Dmitry Ponomarev, Oguz Ergin, Kanad ...
115
Voted
DEXA
2001
Springer
151views Database» more  DEXA 2001»
15 years 5 months ago
Cache Conscious Clustering C3
The two main techniques of improving I/O performance of Object Oriented Database Management Systems(OODBMS) are clustering and buffer replacement. Clustering is the placement of o...
Zhen He, Alonso Marquez
135
Voted
SIGMETRICS
2003
ACM
147views Hardware» more  SIGMETRICS 2003»
15 years 6 months ago
Effect of node size on the performance of cache-conscious B+-trees
In main-memory databases, the number of processor cache misses has a critical impact on the performance of the system. Cacheconscious indices are designed to improve performance b...
Richard A. Hankins, Jignesh M. Patel