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MICRO
2002
IEEE
117views Hardware» more  MICRO 2002»
14 years 9 months ago
Generating physical addresses directly for saving instruction TLB energy
Power consumption and power density for the Translation Lookaside Buffer (TLB) are important considerations not only in its design, but can have a consequence on cache design as w...
Ismail Kadayif, Anand Sivasubramaniam, Mahmut T. K...
DAMON
2007
Springer
15 years 3 months ago
Parallel buffers for chip multiprocessors
Chip multiprocessors (CMPs) present new opportunities for improving database performance on large queries. Because CMPs often share execution, cache, or bandwidth resources among ...
John Cieslewicz, Kenneth A. Ross, Ioannis Giannaka...
93
Voted
HPCA
2009
IEEE
15 years 10 months ago
iCFP: Tolerating all-level cache misses in in-order processors
Growing concerns about power have revived interest in in-order pipelines. In-order pipelines sacrifice single-thread performance. Specifically, they do not allow execution to flow...
Andrew D. Hilton, Santosh Nagarakatte, Amir Roth
DAC
2008
ACM
15 years 10 months ago
Latency and bandwidth efficient communication through system customization for embedded multiprocessors
We present a cross-layer customization methodology for latency and bandwidth efficient inter-core communication in embedded multiprocessors. The methodology integrates compiler, o...
Chenjie Yu, Peter Petrov
VLDB
1992
ACM
161views Database» more  VLDB 1992»
15 years 1 months ago
Performance and Scalability of Client-Server Database Architectures
Recent developments in software and hardware changed the way database systems are built and operate. In this paper we present database architectures based on the Client Server par...
Alex Delis, Nick Roussopoulos