56 search results - page 7 / 12 » Buffering global interconnects in structured ASIC design |
DAC
2005
ACM
15 years 10 months ago
2005
ACM
We demonstrate how to use placement to ameliorate the predicted repeater explosion problem caused by poor interconnect scaling. We achieve repeater count reduction by dynamically ...
FCCM
2007
IEEE
15 years 3 months ago
2007
IEEE
A new platform for reconfigurable computing has an object-based programming model, with architecture, silicon and tools designed to faithfully realize this model. The platform is ...
ASPDAC
2007
ACM
15 years 1 months ago
2007
ACM
Parallel prefix adder is the most flexible and widely-used binary adder for ASIC designs. Many high-level synthesis techniques have been developed to find optimal prefix structures...
DAC
1998
ACM
15 years 1 months ago
1998
ACM
Interconnect-driven optimization is an increasingly important step in high-performance design. Algorithms for buffer insertion have been successfully utilized to reduce delay in gl...
DAC
2002
ACM
15 years 10 months ago
2002
ACM
Rapid approximation of the transient response of high-speed global interconnects is needed to estimate the time delay, crosstalk, and overshoot in a GSI multilevel wiring network....