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ICCAD
2006
IEEE
127views Hardware» more  ICCAD 2006»
15 years 6 months ago
Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization
Parametric yield loss due to variability can be effectively reduced by both design-time optimization strategies and by adjusting circuit parameters to the realizations of variable...
Murari Mani, Ashish Kumar Singh, Michael Orshansky
ISCA
2008
IEEE
136views Hardware» more  ISCA 2008»
14 years 9 months ago
The Design and Performance of a Bare PC Web Server
There is an increasing need for new Web server architectures that are application-centric, simple, small, and pervasive in nature. In this paper, we present a novel architecture f...
Long He, Ramesh K. Karne, Alexander L. Wijesinha
SCP
1998
107views more  SCP 1998»
14 years 9 months ago
A Distributed Arc-Consistency Algorithm
Consistency techniques are an e cient way of tackling constraint satisfaction problems (CSP). In particular, various arc-consistency algorithms have been designed such as the time...
T. Nguyen, Yves Deville
ASPDAC
2009
ACM
145views Hardware» more  ASPDAC 2009»
15 years 4 months ago
High performance on-chip differential signaling using passive compensation for global communication
— To address the performance limitation brought by the scaling issues of on-chip global wires, a new configuration for global wiring using on-chip lossy transmission lines is pr...
Ling Zhang, Yulei Zhang, Akira Tsuchiya, Masanori ...
ICCD
2008
IEEE
175views Hardware» more  ICCD 2008»
15 years 6 months ago
On-chip high performance signaling using passive compensation
— To address the performance limitation brought by the scaling issues of on-chip global wires, a new configuration for global wiring using on-chip lossy transmission lines(T-lin...
Yulei Zhang, Ling Zhang, Akira Tsuchiya, Masanori ...