Sciweavers

372 search results - page 62 / 75
» Building Design Optimization Using Sequential Linear Program...
Sort
View
TSP
2008
131views more  TSP 2008»
14 years 9 months ago
Causal Compensation for Erasures in Frame Representations
In a variety of signal processing and communications contexts, erasures occur inadvertently or can be intentionally introduced as part of a data reduction strategy. This paper disc...
Petros Boufounos, Alan V. Oppenheim, Vivek K. Goya...
ASPDAC
2005
ACM
119views Hardware» more  ASPDAC 2005»
14 years 11 months ago
CMP aware shuttle mask floorplanning
- By putting different chips on the same mask, shuttle mask (or multiple project wafer) provides an economical solution for low volume designs and design prototypes to share the ri...
Gang Xu, Ruiqi Tian, David Z. Pan, Martin D. F. Wo...
GLVLSI
2003
IEEE
146views VLSI» more  GLVLSI 2003»
15 years 3 months ago
A practical CAD technique for reducing power/ground noise in DSM circuits
One of the fundamental problems in Deep Sub Micron (DSM) circuits is Simultaneous Switching Noise (SSN), which causes voltage fluctuations in the circuit power/ground networks. In...
Arindam Mukherjee, Krishna Reddy Dusety, Rajsaktis...
ICASSP
2011
IEEE
14 years 1 months ago
Online Kernel SVM for real-time fMRI brain state prediction
The Support Vector Machine (SVM) methodology is an effective, supervised, machine learning method that gives stateof-the-art performance for brain state classification from funct...
Yongxin Taylor Xi, Hao Xu, Ray Lee, Peter J. Ramad...
PLDI
2003
ACM
15 years 3 months ago
Compile-time dynamic voltage scaling settings: opportunities and limits
With power-related concerns becoming dominant aspects of hardware and software design, significant research effort has been devoted towards system power minimization. Among run-t...
Fen Xie, Margaret Martonosi, Sharad Malik