74 search results - page 10 / 15 » Built-in test generation for synchronous sequential circuits |
VTS
2000
IEEE
15 years 1 months ago
2000
IEEE
We propose a novel BIST technique for non-scan sequential circuits which does not modify the circuit under test. It uses a learning algorithm to build a hardware test sequence gen...
DAC
1995
ACM
15 years 1 months ago
1995
ACM
Abstract A new method for power estimation in sequential circuits is presented that is based on a statistical estimation technique. By applying randomly generated input sequences t...
DAC
1994
ACM
15 years 1 months ago
1994
ACM
Recent results indicate that functional test pattern generation (TPG) techniques may provide better defect coverages than do traditional logic-level techniques. Functional TPG alg...
ICCAD
1995
IEEE
15 years 1 months ago
1995
IEEE
This paper investigates the effect of the controller on the testability of sequential circuits composed of controllers and data paths. It is shown that even when both the controll...
VTS
1998
IEEE
15 years 1 months ago
1998
IEEE
This paper proposes an ATPG technique that reduces power dissipation during the test of sequential circuits. The proposed approach exploits some redundancy introduced during the t...