74 search results - page 7 / 15 » Built-in test generation for synchronous sequential circuits |
ITC
1994
IEEE
15 years 29 days ago
1994
IEEE
ICCD
1997
IEEE
15 years 1 months ago
1997
IEEE
This paper presents a new approach to the automated generation of an initialization sequence for synchronous sequential circuits. Finding an initialization sequence is a hard task...
ITC
1989
IEEE
15 years 1 months ago
1989
IEEE
: The concept of a pseudo-exhaustive test for sequential circuits is introduced in a similar way as it is used for combinational networks. Instead of test sets one has to apply pse...
ICCAD
1994
IEEE
15 years 1 months ago
1994
IEEE
This paper presents a new method of selecting scan
ipops (FFs) in partial scan designs of sequential circuits. Scan FFs are chosen so that the whole circuit can be partitioned in...
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Voted
ICCAD
1996
IEEE
15 years 1 months ago
1996
IEEE
State justification is a time-consuming operation in test generation for sequential circuits. In this paper, we present a technique to rapidly identify state elements (flip-flops)...