18 search results - page 2 / 4 » Bus-aware microarchitectural floorplanning |
ASPDAC
2007
ACM
13 years 10 months ago
2007
ACM
- For modern processor designs in nanometer technologies, both block and interconnect pipelining are needed to achieve multi-gigahertz clock frequency, but previous approaches cons...
DATE
2007
IEEE
14 years 18 days ago
2007
IEEE
Lateral heat conduction between modules affects the temperature profile of a floorplan, affecting the leakage power of individual blocks which increasingly is becoming a larger ...
ASPDAC
2008
ACM
13 years 8 months ago
2008
ACM
In this paper, we present a novel design methodology to combat the ever-aggravating high frequency power supply noise (di/dt) in modern microprocessors. Our methodology integrates ...
DAC
2005
ACM
14 years 7 months ago
2005
ACM
Since across-chip interconnect delays can exceed a clock cycle in nanometer technologies, it has become essential in high performance designs to add flip-flops on wires with multi...
ASPDAC
2006
ACM
14 years 7 days ago
2006
ACM
- Although the emerging three-dimensional integration technology can significantly reduce interconnect delay, chip area, and power dissipation in nanometer technologies, its impact...