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» Bus-aware microarchitectural floorplanning
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ISPASS
2006
IEEE
15 years 3 months ago
Comparing simulation techniques for microarchitecture-aware floorplanning
— Due to the long simulation times of the reference input sets, microarchitects resort to alternative techniques to speed up cycle-accurate simulations. However, the reduction in...
Vidyasagar Nookala, Ying Chen, David J. Lilja, Sac...
ISLPED
2005
ACM
100views Hardware» more  ISLPED 2005»
15 years 3 months ago
Joint exploration of architectural and physical design spaces with thermal consideration
Heat is a main concern for processors in deep sub-micron technologies. The chip temperature is affected by both the power consumption of processor components and the chip layout....
Yen-Wei Wu, Chia-Lin Yang, Ping-Hung Yuh, Yao-Wen ...
CODES
2007
IEEE
15 years 3 months ago
Performance modeling for early analysis of multi-core systems
Performance analysis of microprocessors is a critical step in defining the microarchitecture, prior to register-transfer-level (RTL) design. In complex chip multiprocessor systems...
Reinaldo A. Bergamaschi, Indira Nair, Gero Dittman...